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connection diagrams rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow noise bifet op amp ad743 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product highlights 1. the low offset voltage and low input offset voltage drift of the ad743 coupled with its ultralow noise performance mean that the ad743 can be used for upgrading many applications now using bipolar amplifiers. 2. the combination of low voltage and low current noise make the ad743 ideal for charge sensitive applications such as accelerometers and hydrophones. 3. the low input offset voltage and low noise level of the ad743 provide >140 db dynamic range. 4. the typical 10 khz noise level of 2.9 nv/ ? hz permits a three op amp instrumentation amplifier, using three ad743s, to be built which exhibits less than 4.2 nv/ ? hz noise at 10 khz and which has low input bias currents. 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ? w op27 & resistor ad743 + resistor resistor noise only ad743 & resistor or op27 & resistor r source r source o e input noise voltage ?nv/ hz ( ) (??? ( ?) input noise voltage vs. source resistance features ultralow noise performance 2.9 nv/ ? hz at 10 khz 0.38 m v p-p, 0.1 hz to 10 hz 6.9 fa/ ? hz current noise at 1 khz excellent dc performance 0.5 mv max offset voltage 250 pa max input bias current 1000 v/mv min open-loop gain ac performance 2.8 v/ m s slew rate 4.5 mhz unity-gain bandwidth thd = 0.0003% @ 1 khz available in tape and reel in accordance with eia-481a standard applications sonar preamplifiers high dynamic range filters (>140 db) photodiode and ir detector amplifiers accelerometers product description the ad743 is an ultralow noise precision, fet input, monolithic operational amplifier. it offers a combination of the ultralow voltage noise generally associated with bipolar input op amps and the very low input current of a fet-input device. furthermore, the ad743 does not exhibit an output phase reversal when the negative common-mode voltage limit is exceeded. the ad743s guaranteed, maximum input voltage noise of 4.0 nv/ ? hz at 10 khz is unsurpassed for a fet-input monolithic op amp, as is the maximum 1.0 m v p-p, 0.1 hz to 10 hz noise. the ad743 also has excellent dc performance with 250 pa maximum input bias current and 0.5 mv maximum offset voltage. the ad743 is specifically designed for use as a preamp in capacitive sensors, such as ceramic hydrophones. it is available in five performance grades. the ad743j and ad743k are rated over the commercial temperature range of 0 c to +70 c. the ad743a and ad743b are rated over the industrial temperature range of C40 c to +85 c. the ad743s is rated over the military temperature range of C55 c to +125 c and is available processed to mil-std-883b, rev. c. the ad743 is available in 8-pin plastic mini-dip, 8-pin cerdip, 16-pin soic, or in chip form. ad743 8 top view 1 2 3 7 6 8 5 4 out null nc +v s null ?n +in ? s nc = no connect offset null ad743 ?n +in 8 1 2 3 4 9 10 11 12 13 14 16 nc nc nc output +v s ? s nc nc 15 8 7 6 5 nc offset null nc nc nc nc = no connect 8-pin plastic mini-dip (n) and 8-pin cerdip (q) packages 16-pin soic (r) package
rev. c C2C ad743Cspecifications (@ +25 8 c and 6 15 v dc, unless otherwise noted) ad743j ad743k/b ad743s model conditions min typ max min typ max min typ max units input offset voltage 1 initial offset 0.25 1.0/0.8 0.1 0.5/0.25 0.25 1.0 mv initial offset t min to t max 1.5 1.0/0.50 2.0 mv vs. temp. t min to t max 212 m v/ c vs. supply (psrr) 12 v to 18 v 2 90 96 100 106 90 96 db vs. supply (psrr) t min to t max 88 98 100 88 db input bias current 3 either input v cm = 0 v 150 400 150 250 150 400 pa either input @ t max v cm = 0 v 8.8/25.6 5.5/16 413 na either input v cm = +10 v 250 600 250 400 300 600 pa either input, v s = 5 v v cm = 0 v 30 200 30 125 30 200 pa input offset current v cm = 0 v 40 150 30 75 40 150 pa offset current @ t max v cm = 0 v 2.2/6.4 1.1/3.2 102 na frequency response gain bw, small signal g = C1 4.5 4.5 4.5 mhz full power response v o = 20 v p-p 25 25 25 khz slew rate, unity gain g = C1 2.8 2.8 2.8 v/ m s settling time to 0.01% 6 6 6 m s total harmonic f = 1 khz distortion 4 (figure 16) g = C1 0.0003 0.0003 0.0003 % input impedance differential 1 3 10 10 || 20 1 3 10 10 || 20 1 3 10 10 || 20 w|| pf common mode 3 3 10 11 || 18 3 3 10 11 || 18 3 3 10 11 || 18 w|| pf input voltage range differential 5 20 20 20 v common-mode voltage +13.3, C10.7 +13.3, C10.7 +13.3, C10.7 v over max operating range 6 C10 +12 C10 +12 C10 +12 v common-mode rejection ratio v cm = 10 v 80 95 90 102 80 95 db t min to t max 78 88 78 db input voltage noise 0.1 hz to 10 hz 0.38 0.38 1.0 0.38 m v p-p f = 10 hz 5.5 5.5 10.0 5.5 nv/ ? hz f = 100 hz 3.6 3.6 6.0 3.6 nv/ ? hz f = 1 khz 3.2 5.0 3.2 5.0 3.2 5.0 nv/ ? hz f = 10 khz 2.9 4.0 2.9 4.0 2.9 4.0 nv/ ? hz input current noise f = 1 khz 6.9 6.9 6.9 fa/ ? hz open loop gain v o = 10 v r load 3 2 k w 1000 4000 2000 4000 1000 4000 v/mv t min to t max 800 1800 800 v/mv r load = 600 w 1200 1200 1200 v/mv output characteristics voltage r load 3 600 w +13, C12 +13, C12 +13, C12 v r load 3 600 w +13.6, C12.6 +13.6, C12.6 +13.6, C12.6 v t min to t max +12, C10 +12, C10 +12, C10 v r load 3 2 k w 12 +13.8, C13.1 12 +13.8, C13.1 12 +13.8, C13.1 v current short circuit 20 40 20 40 20 40 ma power supply rated performance 15 15 15 v operating range 4.8 18 4.8 18 4.8 18 v quiescent current 8.1 10.0 8.1 10.0 8.1 10.0 ma transistor count # of transistors 50 50 50 notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 test conditions: +v s = 15 v, Cv s = 12 v to 18 v and +v s = 12 v to +18 v, Cv s = 15 v. 3 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperature, the current doubles every 10 c. 4 gain = C1, r l = 2 k w , c l = 10 pf. 5 defined as voltage between inputs, such that neither exceeds 10 v from common. 6 thc ad743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. all min and max specifications are guaranteed. specifications subject to change without notice.
ad743 rev. c C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (q) . . . . . . . . . . C65 c to +150 c storage temperature range (n, r) . . . . . . . . C65 c to +125 c operating temperature range ad743j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad743a/b . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c ad743s . . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 seconds) . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-pin plastic package: q ja = 100 c/watt, q jc = 50 c/watt 8-pin cerdip package: q ja = 110 c/watt, q jc = 30 c/watt 16-pin plastic soic package: q ja = 100 c/watt, q jc = 30 c/watt esd susceptibility an esd classification per method 3015.6 of mil-std-883c has been performed on the ad743. the ad743 is a class 1 device, passing at 1000 v and failing at 1500 v on null pins 1 and 5, when tested, using an imcs 5000 automated esd tester. pins other than null pins fail at greater than 2500 v. ordering guide package model temperature range option* ad743jn 0 c to +70 c n-8 ad743kn 0 c to +70 c n-8 ad743jr-16 0 c to +70 c r-16 ad743kr-16 0 c to +70 c r-16 ad743bq C40 c to +85 c q-8 ad743sq/883b C55 c to +125 c q-8 ad743jr-16-reel 0 c to +70 c tape & reel ad743kr-16-reel 0 c to +70 c tape & reel *n = plastic dip; r = small outline ic; q = cerdip. metalization photograph contact factory for latest dimensions. dimensions shown in inches and (mm).
ad743 rev. c C4C Ctypical characteristics (@ +25 8 c, v s = +15 v) 0510 15 20 20 5 10 15 0 output voltage swing ?volts r = 10k w positive supply negative supply load supply voltage volts figure 2. output voltage swing vs. supply voltage ?0 ?0 ?0 0 20 40 60 80 100 120 140 10 ? 10 ? 10 ? 10 ? ?0 10 ?1 10 10 ?2 input bias current ?amps temperature ? c figure 5. input bias current vs. temperature ?0 ?0 ?0 0 20 40 60 80 100 120 140 0 40 30 20 10 50 60 70 80 current limit ?ma + output current ?output current temperature ? c figure 8. short circuit current limit vs. temperature 10 100 1k 10k 5 10 15 20 25 30 35 0 load resistance ? w output voltage swing ?volts p-p figure 3. output voltage swing vs. load resistance 0.01 0.1 1 10 100 10k 100k 1m 10m 100m 200 frequency ?hz output impedance ? w figure 6. output impedance vs. frequency (closed loop gain = C1) ?0 ?0 ?0 0 20 40 60 80 100 120 140 3.0 4.0 5.0 6.0 7.0 2.0 temperature ? c gain bandwidth product ?mhz figure 9. gain bandwidth product vs. temperature 0 5 10 15 20 0 51015 20 input voltage swing ?volts r = 10k w ? in +v in load supply voltage volts figure 1. input voltage swing vs. supply voltage 0510 15 20 6 12 9 3 0 quiescent current?ma supply voltage volts figure 4. quiescent current vs. supply voltage 0 ?2 12 common mode voltage ?volts input bias current ?pa ? ? ? 3 6 9 300 200 100 0 figure 7. input bias current vs. common-mode voltage
ad743 rev. c C5C ?0 ?0 ?0 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 slew rate ?volts/ m s temperature ? c figure 11. slew rate vs. temperature (gain = C1) 100 1k 10k 100k 1m 10m 100m 100 80 60 40 20 0 120 power supply rejection ?db frequency ?hz + supply ?supply figure 14. power supply rejection vs. frequency 100 1k 10k 100k 1.0 10 100 10 1m 0.1 1 10m frequency ?hz closed-loop gain = 1 closed-loop gain = 10 noise voltage (referred to input) ?nv hz figure 17. input noise voltage spectral density 05 10 15 20 80 120 130 140 150 100 open-loop gain ?db supply voltage volts figure 12. open-loop gain vs. supply voltage, r load = 2k 35 30 25 20 15 10 5 0 1m 1k 10k 100k frequency ?hz output voltage ?volts p-p r = 2k w l figure 15. large signal frequency response 100 1k 10k 100k 1.0 10 100 10 1 1k frequency ?hz current noise spectral density ?fa/ hz figure 18. input noise current spectral density 100 1k 10k 100k 1m 10m 100m 100 80 60 40 20 0 ?0 100 60 0 20 40 80 ?0 frequency ?hz open-loop gain ?db phase margin ?degrees phase gain figure 10. open-loop gain and phase vs. frequency 100 1k 10k 100k 1m 100 80 60 40 20 0 120 frequency ?hz common-mode rejection ?db v = 10v cm figure 13. common-mode rejec- tion vs. frequency ?40 ?30 ?20 ?10 ?00 ?0 ?0 ?0 thd ?db 100k 10 100 1k 10k frequency ?hz gain = +10 gain = ? figure 16. total harmonic distor- tion vs. frequency
ad743 rev. c C6C Ctypical characteristics (@ +25 c, v s = +15 v) 2.5 3 9 15 21 27 33 39 45 51 57 63 69 2.7 2.9 3.1 3.3 3.5 3.8 number of units input voltage noise ?nv hz figure 19. typical noise distribution @ 10 khz (602 units) figure 20. offset null configuration figure 21. unity-gain follower figure 22a. unity-gain follower large signal pulse response figure 22b. unity-gain follower small signal pulse response ad743 1 m f +v s 0.1 m f 4 v in 2k w 3 2 6 2k w square wave input v out 100pf c l 7 100pf ? s 0.1 m f 1 m f figure 23a. unity-gain inverter figure 23b. unity-gain inverter large signal pulse response figure 23c. unity-gain inverter small signal pulse response
ad743 rev. c C7C op amp performance: jfet vs. bipolar the ad743 is the first monolithic jfet op amp to offer the low input voltage noise of an industry-standard bipolar op amp without its inherent input current errors. this is demonstrated in figure 24, which compares input voltage noise vs. input source resistance of the op27 and the ad743 op amps. from this figure, it is clear that at high source impedance the low current noise of the ad743 also provides lower total noise. it is also important to note that with the ad743 this noise reduction extends all the way down to low source impedances. the lower dc current errors of the ad743 also reduce errors due to offset and drift at high source impedances (figure 25). 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ? w op27 & resistor ad743 + resistor resistor noise only ad743 & resistor or op27 & resistor r source r source o e input noise voltage ?nv/ hz ( ) (??? ( ?) figure 24. total input noise spectral density @ 1 khz vs. source resistance input offset voltage ?mv source resistance ? w adop27g ad743 kn 100 10 1.0 0.1 100 1k 10k 100k 1m 10m figure 25. input offset voltage vs. source resistance designing circuits for low noise an op amps input voltage noise performance is typicaly divided into two regions: flatband and low frequency noise. the ad743 offers excellent performance with respect to both. the figure of 2.9 nv/ ? hz @ 10 khz is excellent for jfet input amplifier. the 0.1 hz to 10 hz noise is typically 0.38 m v p-p. the user should pay careful attention to several design details in order to optimize low frequency noise performance. random air currents can generate varying thermocouple voltages that appear as low frequency noise: therefore sensitive circuitry should be well shielded from air flow. keeping absolute chip temperature low also reduces low frequency noise in two ways: first, the low frequency noise is strongly dependent on the ambient temperature and increases above +25 c. secondly, since the gradient of temperature from the ic package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. low frequency current noise can be computed from the magnitude of the dc bias current ( ~ i n = 2 qi b d f ) and increases below approximately 100 hz with a 1/f power spectral density. for the ad743 the typical value of current noise is 6.9 fa/ ? hz at 1 khz. using the formula, ~ i n = 4 kt / r d f , to compute the johnson noise of a resistor, expressed as a current, one can see that the current noise of the ad743 is equivalent to that of a 3.45 3 10 8 w source resistance. at high frequencies, the current noise of a fet increases proportionately to frequency. this noise is due to the real part of the gate input impedance, which decreases with frequency. this noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude. in any fet input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. this noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pf in value. low noise charge amplifiers as stated, the ad743 provides both low voltage and low current noise. this combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. when dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise. charge (q) is related to voltage and current by the simply stated fundamental relationships: q = cv and i = dq dt as shown, voltage, current and charge noise can all be directly related. the change in open circuit voltage ( d v) on a capacitor will equal the combination of the change in charge ( d q/c) and the change in capacitance with a built in charge (q/ d c).
ad743 rev. c C8C figures 26 and 27 show two ways to buffer and amplify the output of a charge output transducer. both require using an amplifier which has a very high input impedance, such as the ad743. figure 26 shows a model of a charge amplifier circuit. here, amplification depends on the principle of conservation of charge at the input of amplifier a1, which requires that the charge on capacitor c s be transferred to capacitor c f , thus yielding an output voltage of d q/c f . the amplifiers input voltage noise will appear at the output amplified by the noise gain (1 + (c s /c f )) of the circuit. figure 26. a charge amplifier circuit figure 27. model for a high z follower with gain the second circuit, figure 27, is simply a high impedance follower with gain. here the noise gain (1 + (r1/r2)) is the same as the gain from the transducer to the output. resistor r b , in both circuits, is required as a dc bias current return. there are three important sources of noise in these circuits. amplifiers a1 and a2 contribute both voltage and current noise, while resistor r b contributes a current noise of: ~ n = 4 k t r b d f where: k = boltzmans constant = 1.381 x 10 C23 joules/kelvin t = absolute temperature, kelvin (0 c = +273.2 kelvin) d f = bandwidth C in hz (assuming an ideal brick wall filter) this must be root-sum-squared with the amplifiers own current noise. figure 28 shows that these two circuits have an identical frequency response and the same noise performance (provided that c s /c f = r1/ r2). one feature of the first circuit is that a t network is used to increase the effective resistance of r b and improve the low frequency cutoff point by the same factor. ?00 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?00 ?10 ?20 10m 100m 1 10 100 1k 10k 100k frequency ?hz total output noise noise due to r alone b noise due to i alone b decibels referenced to 1v/ hz figure 28. noise at the outputs of the circuits of figures 26 and 27. gain = 10, c s = 3000 pf, r b = 22 m w however, this does not change the noise contribution of r b which, in this example, dominates at low frequencies. the graph of figure 29 shows how to select an r b large enough to minimize this resistors contribution to overall circuit noise. when the equivalent current noise of r b (( ? 4kt )/r) equals the noise of i b ( 2 qi b ), there is diminishing return in making r b larger. 1pa 10pa 100pa 1na 10na 5.2 x 10 10 5.2 x 10 9 5.2 x 10 8 5.2 x 10 7 5.2 x 10 6 input bias current resistance in w figure 29. graph of resistance vs. input bias current where the equivalent noise ? 4kt/r , equals the noise of the bias current 2 qi b to maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. this is represented by the optional resistor r b in figures 26 and 27. as previously mentioned, for best noise performance care should be taken to also balance the source capacitance designated by c b . the value for c b in figure 26 would be equal to c s , in figure 27. at values of c b over 300 pf, there is a diminishing impact on noise; capacitor c b can then be simply a large bypass of 0.01 m f or greater.
ad743 how chip package type and power dissipation affect input bias current as with all jfet input amplifiers, the input bias current of the ad743 is a direct function of device junction temperature, i b approximately doubling every 10c. figure 30 shows the relationship between bias current and junction temperature for the ad743. this graph shows that lowering the junction temperature will dramatically improve i b . ?0 ?0 ?0 0 20 40 60 80 100 120 140 ?1 ?0 10 ? 10 ? 10 ? 10 ? 10 10 10 ?2 junction temperature ?? v = ?5v t = 25? s a + figure 30. input bias current vs. junction temperature the dc thermal properties of an ic can be closely approximated by using the simple model of figure 31 where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance ( q in ?c/watt). = device dissipation = ambient temperature = junction temperature = thermal resistance e junction to case = thermal resistance e case to ambient p in t j jc ca t a where: q q p in ca t a t j jc q q ja q figure 31. a device thermal model from this model t j = t a + q ja pin. therefore, i b can be determined in a particular application by using figure 30 together with the published data for q ja and power dissipation. the user can modify q ja by use of an appropriate clip-on heat sink such as the aavid #5801. q ja is also a variable when using the ad743 in chip form. figure 32 shows bias current vs. supply voltage with q ja as the third variable. this graph can be used to predict bias current after q ja has been computed. again bias current will double for every 10?c. the designer using the ad743 in chip form (figure 33) must also be concerned with both q jc and q ca , since q jc can be affected by the type of die mount technology used. typically, q jc ?s will be in the 3?c to 5?c/watt range; therefore, for normal packages, this small power dissipation level may be ignored. but, with a large hybrid substrate, q jc will dominate proportionately more of the total q ja . 300 0 100 200 5 10 15 t = +25?c a supply voltage e volts = 165?c/w q a = 115?c/w q a = 0?c/w q a j j j figure 32. input bias current vs. supply voltage for various values of q ja figure 33. a breakdown of various package thermal resistances reduced power supply operation for lower i b reduced power supply operation lowers i b in two ways: first, by lowering both the total power dissipation and second, by reducing the basic gate-to-junction leakage (figure 32). figure 34 shows a 40 db gain piezoelectric transducer amplifier, which operates without an ac coupling capacitor, over the 40c to +85c temperature range. if the optional coupling capacitor is used, this circuit will operate over the entire 55c to +125c military temperature range. figure 34. a piezoelectric transducer
ad743 rev. c C10C an input-impedance-compensated, sallen-key filter the simple high pass filter of figure 35 has an important source of error which is often overlooked. even 5 pf of input capacitance in amplifier a will contribute an additional 1% of passband amplitude error, as well as distortion, proportional to the c/v characteristics of the input junction capacitance. the addition of the network designated z will balance the source impedanceCas seen by aCand thus eliminate these errors. figure 35. an input impedance compensated sallen-key filter two high performance accelerometer amplifiers two of the most popular charge-out transducers are hydrophones and accelerometers. precision accelerometers are typically calibrated for a charge output (pc/g).* figures 36a and 36b show two ways in which to configure the ad743 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. the input sensitivity of these circuits will be determined by the value of capacitor c1 and is equal to: d v out = d q out c 1 the ratio of capacitor c1 to the internal capacitance (c t ) of the transducer determines the noise gain of this circuit (1 + c t /c1). the amplifiers voltage noise will appear at its output amplified by this amount. the low frequency bandwidth of these circuits will be dependent on the value of resistor r1. if a t network is used, the effective value is: r1 (1 + r2/r3). figure 36a. a basic accelerometer circuit *pc = picocoulombs g = earth's gravitational constant figure 36b. an accelerometer circuit employing a dc servo amplifier a dc servo-loop (figure 36b) can be used to assure a dc output which is <10 mv, without the need for a large compensating resistor when dealing with bias currents as large as 100 na. for optimal low frequency performance, the time constant of the servo loop (r4c2 = r5c3) should be: time constant 3 10 r 11 + r 2 r 3 ? ? ? ? c 1 a low noise hydrophone amplifier hydrophones are usually calibrated in the voltage-out mode. the circuits of figures 37a and 37b can be used to amplify the output of a typical hydrophone. figure 37a shows a typical dc coupled circuit. the optional resistor and capacitor serve to counteract the dc offset caused by bias currents flowing through resistor r1. figure 37b, a variation of the original circuit, has a low frequency cutoff determined by an rc time constant equal to: time constant = 1 2 p c c 100 w figure 37a. a basic hydrophone amplifier
ad743 rev. c C11C figure 37b. an ac-coupled, low noise hydrophone amplifier figure 37c. a hydrophone amplifier incorporating a dc servo loop where the dc gain is 1 and the gain above the low frequency cutoff (1/(2 p c c (100 w ))) is the same as the circuit of figure 37a. the circuit of figure 37c uses a dc servo loop to keep the dc output at 0 v and to maintain full dynamic range for i b s up to 100 na. the time constant of r7 and c2 should be larger than that of r1 and c t for a smooth low frequency response. the transducer shown has a source capacitance of 7500 pf. for smaller transducer capacitances ( 300 pf), lowest noise can be achieved by adding a parallel rc network (r4 = r1, c1 = c t ) in series with the inverting input of the ad743. balancing source impedances as mentioned previously, it is good practice to balance the source impedances (both resistive and reactive) as seen by the inputs of the ad743. balancing the resistive components will optimize dc performance over temperature because balancing will mitigate the effects of any bias current errors. balancing input capacitance will minimize ac response errors due to the amplifiers input capacitance and, as shown in figure 38, noise performance will be optimized. figure 39 shows the required external components for noninverting (a) and inverting (b) configurations. figure 38. rti voltage noise vs. input capacitance figure 39. optional external components for balancing source impedances
ad743 rev. c C12C outline dimensions dimensions shown in inches and (mm). 8-pin plastic mini-dip (n) 8-pin cerdip (q) packages 16-pin soic (r) package c1433C24C10/90 printed in u.s.a.

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